-- Porta AND 2 entradas

library ieee;
use ieee.std_logic_1164.all;

entity AND_2 is
port(
	A, B : in std_logic;
	S : out std_logic
);
end AND_2;

architecture DT_FLW of AND_2 is
begin
	process(A, B)
	begin
		if ((A = '1') and (B = '1')) then
			S <= '1';
		else
			S <= '0';
		end if;
	end process;
end DT_FLW;